The protection stack for quantum information.

Nine families, one strategy.

Each patent protects the integrity of a quantum state at a different point in the machine. All nine are filed provisional applications.

A gate set by an integer, not a waveform.

Every quantum gate in service today is a precisely shaped microwave pulse — and the precision is the problem. Amplitude that's off by a percent, phase that has drifted since the last calibration: each feeds straight through into gate error, which is why so much of running a quantum processor is recalibrating control electronics that won't hold still.

We move the operation out of the pulse and into the circuit. The gate angle is fixed by an integer winding number — how many times the superconducting phase winds through a physical loop — carried out as a Wilczek–Zee holonomy in a zero-energy "dark" subspace. Because the result depends only on that integer, it shrugs off the exact shape and amplitude of the control waveform: a whole class of control error that the pulse-shaped approach has to calibrate away cancels here by construction. An integer is hard to get a little bit wrong.

This is a different robustness axis from chasing ever-higher pulse fidelity — winding-class robust, not topologically fault-tolerant: the winding still has to be enforced by the control electronics, and adiabaticity and fabrication tolerances still matter. And it runs on clean flux bias, which is exactly what the quiet coil delivers — so the advantage holds as you pack qubits together instead of drowning in crosstalk.

Provisional filed (App. 64/017,790). Analytically derived and simulation-validated; not yet silicon-proven.

Flux control that doesn't spread.

Flux-tunable superconducting chips don't scale cleanly, and the reason is mundane: every flux-bias line is a little antenna that talks to its neighbors. Add qubits and it compounds — each new bias line can disturb every qubit already on the chip, so the calibration burden grows faster than the chip itself. You end up tuning the whole chip against itself.

Our control wiring confines the field instead of broadcasting it. A coaxial solenoid delivers the flux a qubit needs while a matched return cancels the stray field by geometry — an exact, first-order cancellation — so the bias stays local. The crosstalk matrix goes near-diagonal: each qubit feels its own line and almost nothing from anyone else, which turns calibration from a chip-wide fight into N independent jobs you can run in parallel.

Against a conventional bias wire that's a ≥300× reduction in crosstalk, validated in field solvers. It's also a manufacturing non-event — the solenoid is wound in the standard trilayer process with no extra mask steps. To be precise about scope: this confines uniform, laboratory flux noise; it isn't a fix for surface-spin, dielectric, or quasiparticle noise, and it's validated in simulation, not yet silicon.

Provisional filed (App. 64/022,566), eight related inventions. EM/field-solver validated; not yet silicon-proven.

Forecast the wall before you scale into it.

Adding qubits is the industry's answer to almost everything, but it only works if you're truly below the error-correction threshold everywhere on the chip. Real processors aren't uniform — a few bad couplers or one noisy region pull the effective threshold down, by roughly 25% in our simulations. And what trips a logical qubit isn't the chip's average error rate; it's the weakest path through the code. Hot spots make that path far worse than the average, so a chip can clear the "below threshold" bar on its average while the path that actually decides the outcome is already over the line. Add qubits expecting the exponential payoff, and the logical error rate flattens instead of falling — qubits spent, no return.

The miss is in what gets measured. A logical failure isn't "a lot of errors" — it's a connected error chain spanning the code, and average error rates and raw defect counts can't see one forming. We model every interface as a finite budget, capacity against load, and watch the saturation map: where the correction burden is concentrating. That signal flags a forming failure earlier than raw defect count does — in time to steer correction toward the interfaces nearest the line.

It's vendor-agnostic control-plane software that runs on the syndrome and decoder data a code already produces, on superconducting, ion-trap, or neutral-atom hardware. It doesn't wait on our own chips to ship.

Provisional filed (App. 64/070,628). Results are simulation-validated, not yet silicon-proven.

A verdict you can hand a customer.

The whole point of a quantum computer is that a classical one can't keep up — which makes it challenging to audit its work. Every answer it returns carries two unanswered questions: is the hardware still behaving the way it should, and did it actually do something a classical machine couldn't? Today both collapse into a single fidelity score — a headline number that says "good enough" but hides the breakdown: where the errors actually are, whether the device has drifted or hit a limit, and whether the result was beyond classical at all.

We replace the one number with a diagnosis. For every classical explanation of what the device did, we weigh the two prices the diagram plots — cost, the classical resource it must spend (including the hidden bookkeeping a classical model has to invent), and distortion, the error that explanation has to accept. Where the cheapest classical explanation lands against the budget sorts the device into a four-way verdict: healthy and in spec, near a limit, drifting, or genuinely quantum. That last verdict has a hard backstop — once a device violates a Bell test, no classical model can match it, and the result can't be argued down.

The output of this assessment is the product: a four-way health read with a live drift monitor, and a signed certificate that a workload was hard for a classical machine. It's vendor-agnostic and runs on the data the hardware already emits.

Provisional filed (App. 64/070,738).

The trust layer, four families deep.

The verdict above is only as good as the diagnostics underneath it — so in July 2026 we filed the diagnostics too. Three families take the trust layer from a report format to a protected measurement methodology: what the streams say when you read them together, what kind of correlation a channel is carrying, and which physical mechanism is eating the budget.

Sign off the chip before it exists.

Everything above measures a machine that has already been built. The newest layer moves the same physics to the other side of fabrication. Quantum chip layout today is constrained by empirical tolerance windows and tunable cost-function weights — margins chosen from experience, checked by characterize-and-iterate after the fact. The result is exactly what you'd expect: first-pass yield is a gamble, and every fabrication run is part of the design loop.

We synthesize the layout under derived limits instead. Pairwise coupling between placed elements is computed from a physical field-overlap objective; placement, routing, winding topology, and frequency allocation are then adjusted until every parasitic channel sits below a closed-form threshold from our cost model, and every operating frequency clears the integer threshold rule that AT-008 uses for attribution. The layout that comes out carries a per-channel certificate — channel, threshold, computed value, margin — and goes to the mask file certified.

The field is converging on this idea — the mid-2026 "fabless quantum" roadmap proposes physics-derived design signoff as a concept. We filed with the closed-form thresholds and the working constraint loop. And the layer composes with the rest of the stack: AT-008's attribution picks each channel's threshold, and the certificate primes AT-007's monitoring baseline the day the chip comes back.

Provisional filed (App. 64/105,110), 2026-07-04. Synthesis flow specified with closed-form constraints; not yet exercised on a fabricated device.

The frontier: engineering the vacuum boundary itself.

The deepest layer of the same idea is the vacuum boundary. A topological-insulator surface carries a protected sea of Dirac electrons; place a switchable magnetic boundary on it and you can shape the quantum vacuum right at that surface. We hold a provisional on two modes of one platform — and we're candid that this is the exploratory edge of the program.

Driven — the magnetic boundary oscillated by a piezo — the surface emits pairs of frequency-entangled electrons: a fermionic dynamical Casimir effect, predicted to run orders of magnitude faster than its photonic cousin, which makes it a candidate on-chip entanglement source. Held static, the same surface produces a repulsive Casimir force: a self-correcting gap that resists nanoscale stiction, useful for keeping MEMS/NEMS structures and processor gaps from collapsing.

The novelty rests on the entangled-pair source, where the prior art is thinnest; the static repulsive effect sits closer to the recent literature. This is option-value IP, not a near-term product — but it carries the same strategy, protecting the quantum state, all the way down to the vacuum.

Provisional filed (App. 64/070,728). Exploratory; physics is analytical, no device built.