Error correction · QEC runtimeAT-003

Predict logical failure before it spans the array.

Saturation-aware adaptive QEC runtime

Adding qubits is the industry's answer to almost everything, but it only works if you're truly below the error-correction threshold everywhere on the chip. Real processors aren't uniform — a few bad couplers or one noisy region pull the effective threshold down, by roughly 25% in our simulations. And what trips a logical qubit isn't the chip's average error rate; it's the weakest path through the code. Hot spots make that path far worse than the average, so a chip can clear the "below threshold" bar on its average while the path that actually decides the outcome is already over the line. Add qubits expecting the exponential payoff, and the logical error rate flattens instead of falling — qubits spent, no return.

The miss is in what gets measured. A logical failure isn't "a lot of errors" — it's a connected error chain spanning the code, and average error rates and raw defect counts can't see one forming. We model every interface as a finite budget, capacity against load, and watch the saturation map: where the correction burden is concentrating. That signal flags a forming failure earlier than raw defect count does — in time to steer correction toward the interfaces nearest the line.

It's vendor-agnostic control-plane software that runs on the syndrome and decoder data a code already produces, on superconducting, ion-trap, or neutral-atom hardware. It doesn't wait on our own chips to ship.

FORECAST THE WALL More qubits only pay off below threshold — and real chips aren't uniform. worse better logical error rate add more qubits → wall hits ~25% sooner than the average says below threshold — exponential payoff real chip — heterogeneous capacity Saturation Monitor flags it here — before the array fails Vendor-agnostic control-plane software — runs on the syndrome data any code already produces, and steers correction toward the interfaces nearest the line.

Provisional filed (App. 64/070,628). Results are simulation-validated, not yet silicon-proven.

Inside error correction

The saturation map

near-saturated path — flagged before it spans cell shade = budget load · bright = near capacity
Each interface carries a finite budget; a logical failure is a connected, near-saturated path spanning the code — visible on the map as it forms.

Early warning

failure threshold early warning saturation score rises before the logical error
A per-stabilizer saturation score rises ahead of the logical error — beating raw defect count — leaving time to steer correction.
The science

A fresh reduction-to-practice in simulation.

The saturation/percolation picture of the fault-tolerance threshold, the predictive-observable results, and the information-theoretic early-warning divergence were demonstrated on toric-code simulations under standard decoding. Carry-over to full circuit-level noise is the next validation step.

References E. S. Brooke, "Fault Tolerance as Admissibility Saturation" and "Markov Breakdown" (2026). Logical failure as a spanning saturation transition; per-stabilizer saturation as a failure predictor; a variance early-warning signal diverging at the breakdown point.
Patent-pending · provisional filed Reduction-to-practice in toric-code simulation Circuit-level noise: next step
Work with us

Running error correction at scale?

Layer saturation-aware monitoring onto your decoder stack.
ethan@admissibletech.com